In computers, a cache memory is a fast memory located close to the CPU that holds the most recently accessed code or data. When the data is not found in the cache a cache miss occurs and data is retrieved from the main memory, and put into the cache. During this time the CPU is interrupted and placed in a wait state until the data is available.
The CPU sends an address into the cache to examine the cache, which contains words stored in the cache. The data stored in each cell is commonly referred to as a "tag" and a tag word is formed by a row of tags or memory cells. If the word addressed by the CPU is found in the cache, it is read from the cache. If not, the main memory is addressed to read the word. A block of words containing the word just accessed is then transferred from the main memory to the cache.
The cache memory receives addresses from the CPU and performs a search and comparison with addresses stored in the cache. To perform this comparison in parallel at high speed, an associative or content addressable memory (CAM) is required. The time to access information in a memory can be reduced drastically if the stored data can be identified by the content rather than by an address. CAMs or associative memories are used extensively in cache memories and translation look-aside buffers (TLB). Generally, CAMs are used in caches to translate physical addresses to data and in TLBs to translate virtual addresses to physical addresses. CAMs are an extremely powerful tool for associative data processing.
Speed is important in cache memories because, in general, a cache memory should be a factor of 5to 10faster than the main memory. To date, only SRAMs have the speed necessary for cache memories and the like.
In the prior art, most cache memories are composed of an array of SRAMs. SRAM type of memory cells have the required speed but they are volatile memories. In the prior art, SRAM cells are formed in an array with all of the comparison and match detection circuitry positioned at the periphery or otherwise external to the array. Also, SRAM based CAMs cannot be turned off at the cell but masking must be take place in the periphery, which results in wasted power. Further, different memory cells are generally used in the main memory so that the cache memory and the main memory require different processing and fabrication steps.
Accordingly it is highly desirable to provide cache memories which overcome these problems.